Main Article Content
This article describes an extraction technique of input and output impedances of integrated circuits (ICs) implemented onto the printed circuit boards (PCBs). The feasibility of the technique is illustrated with a proof-of-concept (POC) constituted by two ICs operating in a typically transmitter-receiver (Tx-Rx) circuit. The POC system is assumed composed of three different blocks of emitter signal source, load and interconnect passive network. This latter one is assumed defined by its chain matrix known from its electrical and physical characteristics. The proposed impedance extraction method is elaborated from the given signals at the transmitter output and receiver input. The terminal access impedances are formulated in function of the parameters of the interconnect system chain matrix. The feasibility of the method is checked with a passive circuit constituted by transmission lines driven by voltage source with RL-series network internal impedance and loaded at the output by the RC-parallel network. Good correlation between the access impedance reference and calculated is found.
Authors who publish with this journal agree to the following terms:
- Authors retain copyright and grant the journal right of first publication with the work simultaneously licensed under a Creative Commons Attribution License that allows others to share the work with an acknowledgement of the work's authorship and initial publication in this journal.
- Authors are able to enter into separate, additional contractual arrangements for the non-exclusive distribution of the journal's published version of the work (e.g., post it to an institutional repository or publish it in a book), with an acknowledgement of its initial publication in this journal.
- Authors are permitted and encouraged to post their work online (e.g., in institutional repositories or on their website) prior to and during the submission process, as it can lead to productive exchanges, as well as earlier and greater citation of published work (See The Effect of Open Access).
International Technology Roadmap for Semiconductors (ITRS) Reports, 2017, Available Online ,
A. Shaughnessy, H. Holden and S. Las Marias, "Three perspectives on HDI design and manufacturing success," The PCB Design Magazine, Nov. 2017, pp. 22-27.
C. F. Yee, A. B. Jambek and A. A. Al-Hadi, "Advantages and Challenges of 10-Gbps Transmission on High-Density Interconnect Boards," Journal of Electronic Materials, vol. 45, no. 6, June 2016, pp. 3134–3141.
H. Husby, "High Density Interconnect," White Paper, Data Response, Available Online .
P. Kapur, G. Chandra, James P. McVittie, and K. C. Saraswat, "Technology and reliability constrained future copper interconnects–part II: performance implications," IEEE Trans. Electron. Devices, vol. 49, no. 4, pp. 598–604, April 2002.
S. A. Jawed, S. S. Afridi, M. A. Anjum, and K. Khan, "IO circuit design for 2.5D through-silicon-interposer interconnects: IO Circuit Design for 2.5D through-silicon-interposer," Int. J. Circ. Theor. Appl., Vol. 45, No. 3, Mar. 2017, pp. 376–391.
R. M. Averill, K. G. Barkley, M. A. Bowen, P. J. Camporese, A. H. Dan-sky, R. F. Hatch, D. E. Hoffman, M. D. Mayo, S. A. McCabe, T. G. McNamara, T. J. McPherson, G. A. Northrop, L. Sigal, H. H. Smith, D. A. Webber, and P. M. Williams, "Chip integration methodology for the IBM S/390 G5 and G6 custom microprocessors," IBM J. Res. Develop., vol. 43, no. 5/6, pp. 681-706, Sep./Nov. 1999.
C. Armenti, "The impact of HDI on PCB power distribution," The PCB Design Magazine, Nov. 2017, pp. 28-36.
T. Eudes, B. Ravelo and R. Al Hayek, "Assessment of 50%-Propagation-Delay for Cascaded PCB Non-Linear Interconnect Lines for the High-Rate Signal Integrity Analysis," Advanced Electromagnetics (AEM), Vol. 2, No. 1, Feb. 2013, pp. 1-14.
N. Liu, M. Nakhla and Q.-J. Zhang, "Time domain sensitivity of high-speed VLSI interconnects," Int. J. Circ. Theor. Appl., Vol. 22, No. 6, Nov./Dec. 1994, pp. 479–511.
R. Archambeault, C. Brench, and S. Connor, "Review of Printed-Circuit-Board Level EMI/EMC Issues and Tools," IEEE Trans. Electromagnetic Compatibility, vol. 52, no. 2, pp. 455-461, May 2010.
C. Schuster, and W. Fichtner, "Parasitic Modes on Printed Circuit Boards and their Effects on EMC and Signal Integrity," IEEE Trans. Electromagnetic Compatibility, vol. 43, no. 4, pp. 416-425, Nov. 2001.
F. Jun, Y. Xiaoning, J. Kim, B. Archambeault, and A. Orlandi, "Signal integrity design for high-speed digital circuits: Progress and directions," IEEE Trans. Electromagnetic Compatibility, vol. 52, no. 2, pp. 392-400, May 2010.
A. Ruan, J. Yang, L. Wan, B. Jie, and Z. Tian, "Insight into a generic interconnect resource model for Xilinx Virtex and Spartan series FPGAs," IEEE Trans. CAS-II: Express Briefs, vol. 60, no. 11, Nov. 2013, pp. 801-805.
Y. Han and D. J. Perreault, "Analysis and Design of High Efficiency Matching Networks," IEEE Trans. on Power Electr., vol. 21, no. 5, pp. 1484-1491, September 2006.
Y. Yamagami, Y. Tanji, A. Hattori, Y. Nishio and A. Ushida, "A reduction technique of large-scale RCG interconnects in the complex frequency domain," Int. J. Circ. Theor. Appl., vol. 32, no. 6, Nov./Dec. 2004, pp. 471–486.
"High-Speed Board Layout Guidelines," Stratix II Device Handbook, vol. 2, Altera Corporation 11, pp. 1-32, May 2007.
C.‐S. Hoo, K. Jeevan and H. Ramiah, "Cost reduction in bottom‐up hierarchical‐based VLSI floor planning designs," Int. J. Circ. Theor. Appl., vol. 43, no. 3, Mar. 2015, pp. 286-306.
B. Ravelo, "Behavioral model of symmetrical multi-level T-tree interconnects," Progress In Electromagnetics Research B, vol. 41, 2012, pp. 23-50.
T. Eudes and B. Ravelo, "Analysis of multi-gigabits signal integrity through clock H-tree," Int. J. Circ. Theor. Appl., vol. 41, no. 5, May 2013, pp. 535-549.
B. Ravelo, "Modelling of asymmetrical interconnect T-tree laminated on flexible substrate," Eur. Phys. J. Appl. Phys., vol. 72, no. 2 (20103), November 2015, pp. 1-9.
B. Ravelo, "Theory on asymmetrical coupled-parallel-line transmission and reflection zeros," Int. J. Circ. Theor. Appl., vol. 45, no. 11, Nov. 2017, pp. 1534–1551.
"Performing Signal Integrity Analyses," Tutorial, TU0113 (v1.3), Mar. 2008, Available online, Accessed 21 Feb. 2018.
Fundamentals of Signal Integrity, Tektronix Application note, Available online, Accessed 21 Feb. 2018.
"Diagnosys PinPoint II R: The leading bench-top PCB test system," Accessed 21 Feb. 2018.
M. Gaudion, "Controlled Impedance Test," AP149, Accessed 21 Feb. 2018.
"Board-Level Design for Testability," Accessed 21 Feb. 2018.
B. Neal, "Design for Testability – Test for Designability," The Board Authority, pp. 56-60, Sept. 2000.
"ICT, In Circuit Test Tutorial," Accessed 21 Feb. 2018.
Z. Xu, Y. Liu, B. Ravelo and O. Maurice, "Modified Kron's TAN Modeling of 3D Multilayer PCB," Proc. of 11th International Workshop on Electromagnetic Compatibility of Integrated Circuits, EMC Compo 2017, St. Petersburg, Russia, 4-8 July 2017, pp. 242-247.
Z. Xu, Y. Liu, B. Ravelo and O. Maurice, "Multilayer Power Delivery Network Modeling with Modified Kron's Method (MKM)," Proc. of 16th Int. Symposium on Electromagnetic Compatibility (EMC) Europe 2017, Angers, France, 4-8 Sept. 2017, pp. 1-6.
Y. Shang, C. Li, and H. Xiong, "One method for via equivalent circuit extraction based on structural segmentation," Int. J. Computer Science Issues, vol. 10, no. 3, pp. 18-22, May 2013.
HFSS/ANSYS®, Accessed 21 Feb. 2018,