Plasmonic Logic Gates at Optimum Optical Communications Wavelength

This paper displays a design that realizes all optical logic gates (NOT, AND, OR, NAND, NOR, XOR, XNOR) and consisting of one nanoring and four strips Operates on the principle of resonance. the proposed design works at the wavelength of 1550 nm using insulator-metal-insulator (IMI) plasmonic waveguide. The basic principle of the operation of these gates is input and control signals’ constructive and destructive interference. The proposed transmission threshold’s value is 0.25 between OFF state and ON state. The proposed design has small dimensions (300 nm × 300 nm) and can realize seven logic gates with maximum transmission 134% at NOT gate, 223% at OR gate, 134% at NAND gate and 223% at XNOR gate where the design is optimum and the modulation depth is very high because it’s ranges in all gates more than 90%. The proposed structure contributes in building nanocircuits for integrated photonic circuits and optical signal processing.


I. INTRODUCTION
In previous years, clear advances have emerged in the field of All-optical devices due to research efforts and studies of surface plasmon polaritons (SPPs) field [1]. SPP All-optical devices, which represent applications of plasmonic phenomena, were able to overcome the problems found in optical devices such as the diffraction limit that appears when the device's size is close to or greater than the light's wavelength that limits the minimum chip size [2], as well as the problems of electronic devices such as low data rate, low speed and heat generation that rises as a result of increased resistance [3], [4], which leads to inability to apply the principle of high frequency and transfer data at a high rate. SPPs represents the interaction between free electrons of metals and electromagnetic waves and propagation happens on metal-dielectric interface as the electrons oscillate at the light frequencies [5], [6], [7]. Various plasmonic devices such as resonators [8], splitters [9], modulators [10], switches [11], [12], and logic gates [13], [14] were manufactured. Lots of studies have been created on logic gates, so different designs have been created made of different materials and with different geometric shapes and resonance frequencies, each design achieves a certain number of logic gates such as one design it's dimensions (2.4 µm × 3 µm) provides one logic gate when the wavelength is 850 nm [15], one design it's dimensions (760 nm × 600 nm) provides three logic gates when the wavelength is 1535 nm [16], two design their dimensions (1220 nm × 1120 nm) provide four logic gates when the wavelength is 525 nm [17], two design their dimensions (750 nm × 900 nm and 1.5 µm × 1.8 µm) provide three logic gates when the wavelength is 1535 nm [18], one design it's dimensions (400 nm × 400 nm) provides seven logic gates when the wavelength is 1550 nm [3], and one design it's dimensions (400 nm × 380 nm) provides seven logic gates when the wavelengths is 900 nm and 1330 nm [19]. In this paper, we suggest a new design with small dimensions (300 nm × 300 nm) that could achieve the seven logic gates (NOT, AND, OR, NAND, NOR, XOR, XNOR) where maximum transmission 134% at NOT gate, 223% at OR gate, 134% at NAND gate, and 223% at XNOR gate where the design is optimum design based on modulation depth equation and its resonance frequency at the wavelength of 1550 nm and with a transmission threshold 0.25 for all gates. The design efficiency and performance of the gates were measured by three standards: transmission, contrast ratio, and modulation depth. We organized this paper as following: Section 2 explains the structure design, theoretical concept and material. Section 3 explains the performance and simulation results for plasmonic logic gates. Section 4 explains the difference between the proposed work and previous research. Section 5 explains the concluding remarks.

II. THEORETICAL CONCEPT AND STRUCTURE LAYOUT
The proposed design that was designed to realize the seven plasmonic logic gates is illustrated at Fig. 1. This design consists of one nanoring resonator in the middle and four straight strips around it. The nanoring resonator and strips formed from silver as a conductor, while the rest of the design made of low refractive index dielectric material (crystal). Since all the seven gates have same parameters, materials and dimensions in their structure, Table I provides the proposed design's dimensions.  All optical logic gates realized in one design by relying on insulator -metal -insulator (IMI) plasmonic waveguides in lieu of metal -insulator -metal (MIM) plasmonic waveguides because of its advantages such as less propagation loss, less confinement, high propagation length, high quality factor, low coupling loss and easy fabrication [3]. The refractive index of low refractive index dielectric material (crystal) is equal to 1.926 [20], while the silver used in the composition of the nanoring resonator and the four strips was according to Johnson and Christie's data. The value of the nanoring resonance wavelength λsp is calculated by the equation below [3].
Where the effective refractive index is symbolized by neff and the larger diameter of the nanoring is symbolized by D. Given that the wavelength of 1550 nm is the best option in optical communication applications, it was adopted in this research where the proposed design was designed with specific dimensions and types of materials that fit the chosen wavelength of resonance. For the transverse magnetic mode (TM), the dispersion equation is given as [3], [21].
Metal dielectric constant is symbolized by εm, dielectric wave number is symbolized by kd, the insulator dielectric constant is symbolized by εd, metal wave number is symbolized by km, and the thickness of the metal is symbolized by W.
Free space wave number is symbolized by k0 and the propagation constant is symbolized by β which is represented by neff of the waveguide such as [3], [16].
Two-dimensional (2-D) Finite element method (FEM) is method in which performance of the system is measured and Maxwell's equations are solved numerically. convolutional perfectly matched layer used as the absorbing boundary condition simulate the computational area. The proposed design has four ports, two of which are for the input, one for the control and one for the output, which are specified by the type of gate. A polarized waveform (TM) with an electromagnetic field for the EX, EY and HZ components Is exposed to input ports. The proposed design achieves all seven logic gates with the same dimensions and materials for all gates. A transmission threshold of 0.25 was chosen between ON state and OFF state [22]. Performance of logic gates and proposed design is measured by three standard: The first standard is the transmission T, which is measured for the two states of ON and OFF [3]. The transmission threshold is a criterion for determining the type of the state where the transmission value must be greater than 0.25 for all gates in ON state [22]. the transmission value is measured by the equation [15], [16].
Where the transmission is symbolized by T, the output optical power is symbolized by Pout, and optical power of input that entered into control port or single input port, which is 1 µW, is symbolized by Pin.
The second standard is optical power's contrast ratio (CR) in ON-OFF state at the output port that is described as shown in Table II [23], so when the difference in power is large, the performance of the gate is high. the following equation explains the mechanism for calculating the contrast ratio [16], [19].  The third standard is the modulation depth (MD) that is described as shown in table III, where the efficiency of the design dimensions is measured according to the following equation [24], [25].
. +,(!01) The maximum value of the transmission in ON state is symbolized by TON(max) and the transmission's minimum value in OFF state is symbolized by TOFF(min). Surface resonance occurs because of the interaction between the metallic plasmonic nanoring and the strips due to the coupling of the electromagnetic fields between the nanoring resonator and the strips. Transmission power depends on the dimensions of the parameters of the design and their distance from each other and the type of materials the design is made of, as one design with the same dimensions and materials achieves all gates, but the difference between one gate and another lies in manipulating and changing the ports, as well as changing the angles of input power in control and input ports to form constructive and destructive interference which submit to the incident wave phase as in the equation below [26].
m represents a number greater than 0 describing the phase of the interference, the effective refractive index is symbolized by neff, thickness of the metal is symbolized by d, phase is symbolized by θ, and incident wavelength is symbolized by λ.
It is worth noting that changing the phase angle of the signals that inputted to the control port and the input port need a precontroller circuit before entering the structure, and this is not discussed in this paper.

III. PROPOSED ALL OPTICAL LOGIC GATES
Trial-and-error is the method used in choosing input, control and output ports for all logic gates in order to get the best transmission, contrast ratio and modulation depth. The transmission light that the input and control ports are exposed to in all optical gates has a wavelength range from 800 nm to 2000 nm.

A. PLASMONIC NOT GATE
NOT logic gate acts like a reflector for its input signal as shown in the truth table at the Fig. 2 (a). Fig. 2 (b) shows the circuit symbol. To achieve NOT gate port 3 was considered as input port, port 1 as first control port, port 2 as second control port and port 4 as output port in NOT gate design as shown in Fig. 1. Arranging the ports in this way leads to destructive and constructive interference between the control and input signals. The state of output port is ON which is higher than the transmission threshold when input port's state is OFF and control ports are in ON state and in the same phase. When input port's state is ON and the control ports are also ON state and operate with a phase difference for all ports, the output port's state will be OFF which is less than the value of the transmission threshold. Proposed plasmonic NOT gate's transmission spectra are shown at Fig. 2 (c). Magnetic field distribution of the first and the second cases are shown at Fig.  3 (a) and Fig. 3 (b), respectively. Table IV shows the value of  transmission and input phase, table V shows contrast ratio's  value, and table VI shows the value of the modulation depth. The contrast ratio is high because of ( 56789:(;<=) ) is higher than ( 56789>>(;?@) ) and the contrast is large between the values of these optical powers. Thus, the performance of this proposed gate is excellent and efficient. The modulation depth is very high because the variance between the maximum transmission in ON state and the minimum transmission in OFF state is very large. As a result, the dimensions of the proposed design are excellent and optimum.

B. PLASMONIC AND GATE
AND logic gate has four logical states, three of which are OFF and one is ON. If all the inputs are ON, the output is ON, otherwise the output is OFF as shown in the truth table in Fig.  4 (a). Fig. 4 (b) shows the circuit symbol. To achieve AND gate port 1 was considered as the first input port, port 2 as the second input port, port 4 as control port and port 3 as output port in the proposed design as shown in Fig. 1. Constructive interference only occurs when all the inputs are ON and in the same phase where the transmission value is higher than the transmission threshold value. If the two inputs are opposite, the interference is destructive. The control port is always ON and at angle of 0°. Proposed plasmonic AND gate's transmission spectra are shown in Fig. 4 (c). Magnetic field distribution of all cases is illustrated in Fig. 5

C. PLASMONIC OR GATE
OR logic gate has four logical states, three of which are ON and one is OFF. If all the inputs are OFF, the output is OFF, otherwise the output is ON as shown in the truth table in Fig.  6 (a). Fig. 6 (b) shows the circuit symbol. To achieve OR gate port 1 was considered as the first input port, port 2 as the second input port, port 3 as the control port and port 4 as the output port in the proposed design as shown in Fig. 1.
Constructive interference occurs If one or all of the inputs are ON state where the input and control port signal in same phase. the control port is always ON and at angle of 0°. Proposed plasmonic OR gate's transmission spectra are illustrated in Fig. 6 (c). Magnetic field distribution of all cases is illustrated in Fig. 7 (a), Fig. 7 (b), Fig. 7 (c), and Fig. 7 (d), respectively. Table X shows the value of transmission, table XI shows the value of the Contrast Ratio, and table XII shows the value the modulation depth. The contrast ratio is medium because the contrast between (P ABC8DE(FGH) ) and (P ABC8DII(FJK) ) is not large enough. Thus, the performance of this proposed gate is good and efficient. The modulation depth is very high because the variance between the maximum transmission in ON state and the minimum transmission in OFF state is very large. As a result, the dimensions of the proposed design are excellent and optimum.

D. PLASMONIC NAND GATE
NAND logic gate has four logical states, three of which are ON and one is OFF. If all the inputs are ON, the output is OFF, the other three cases are all ON. This gate is opposite to the logic gate AND as shown in the truth table in Fig. 8 (a). Fig. 8 (b) shows the circuit symbol. To achieve NAND gate port 2 was considered as the first input port, port 3 as the second input port, port 1 as the control port and port 4 as output port in the proposed design as shown in Fig. 1. Both constructive and destructive interference play a role in achieving the function of this gate because of the phase difference between the transmitted signals. The control port is always ON and at angle of 0°. Proposed plasmonic NAND gate's transmission spectra are shown in Fig. 8 (c). Magnetic field distribution of all cases is illustrated in Fig. 9 (a), Fig. 9 (b), Fig. 9 (c), and Fig. 9 (d), respectively. Table XIII shows the value of transmission, table  XIV shows the value of the Contrast Ratio, and table XV shows the value of the modulation depth. The contrast ratio is medium because the contrast between ( 56789:(;<=) ) and ( 56789>>(;?@) ) is not large enough. Thus, the performance of this proposed gate is good and efficient. The modulation depth is very high because the variance between the maximum transmission in ON state and the minimum transmission in OFF state is very large. As a result, the dimensions of the proposed design are excellent and optimum.      Fig. 10 (a). Fig. 10 (b) shows the circuit symbol. To achieve NOR gate port 2 was considered as the first input port, port 3 as the second input port, port 1 as the control port and port 4 as the output port in the proposed design as shown in Fig. 1. The first case of the NOR gate is very similar in its operation to the first case of NOT gate, while the rest of the cases can be achieved by destructive interference resulting from the difference in phase. The control port is always ON and at angle of (180°). Proposed plasmonic NOR gate's transmission spectra are illustrated in Fig. 10 (c). Magnetic field distribution of all cases is illustrated in Fig. 11 (a), Fig. 11 (b), Fig. 11 (c), and Fig. 11 (d), respectively. Table XVI shows the value of transmission, table  XVII shows the value of the Contrast Ratio, and table XVIII Shows the value of the modulation depth. The contrast ratio is medium because the contrast between ( 56789:(;<=) ) and ( 56789>>(;?@) ) is not large enough. Thus, the performance of this proposed gate is moderate. The modulation depth is very high because the variance between the maximum transmission in ON state and the minimum transmission in OFF state is very large. As a result, the dimensions of the proposed design are excellent and optimum.

F. PLASMONIC XOR GATE
XOR logic gate has four logical states, two of which are ON and two are OFF. If the two inputs are opposite with value (0 1, 1 0) then the output is ON, but if the two inputs are the same (00, 11) then the output is OFF as shown in the truth table in Fig. 12 (a). Fig. 12 (b) shows the circuit symbol. To achieve XOR gate port 1 was considered as the first input port, port 2 as the second input port, port 3 as the control port and port 4 as the output port in the proposed design as shown in Fig. 1. Destructive interference occurs in the fourth case only, resulting in OFF state. In second and third cases constructive interference occurs, resulting in ON state. The control port is always ON and at angle of (0°). Proposed plasmonic XOR gate's transmission spectra are illustrated in Fig. 12 (c).
Magnetic field distribution of all cases is illustrated in Fig. 13 (a), Fig. 13 (b), Fig. 13 (c), and Fig. 13 (d), respectively. Table  XIX shows the value of transmission, table XX shows the value of the Contrast Ratio, and table XXI Shows the value the modulation depth. The contrast ratio is medium because the contrast between ( 56789:(;<=) ) and ( 56789>>(;?@) ) is not large enough. Thus, the performance of this proposed gate is good and efficient. The modulation depth is very high because the variance between the maximum transmission in ON state and the minimum transmission in OFF state is very large. As a result, the dimensions of the proposed design are excellent and optimum.

G. PLASMONIC XNOR GATE
XNOR logic gate has four logical states, two of which are ON and two are OFF. If the two inputs are the same with the value (00, 11) then the output is ON, but if the two inputs are opposite with the value (01, 10) then the output is OFF as shown in the truth table in Fig. 14 (a). Fig. 14 (b) shows the circuit symbol. To achieve XNOR gate Port 2 was considered as the first input port, port 3 as the second input port, port 1 as the control port and port 4 as the output port in the proposed design as shown in Fig. 1. XNOR gate ports are the same as the ports of NOR and NAND gates, but the difference lies in the angle of the input signals to achieve the desired gate. The first case of this gate is similar to the first case of the NOT gate. In the second and third cases, destructive interference occurs between control and input signals because of the phase difference leading to a transmission value less than the transmission threshold value. In fourth case, constructive interference between input and control signals leads to a transmission value greater than the transmission threshold value. The control port is always ON and at angle of (180°). Proposed plasmonic XNOR gate's transmission spectra are illustrated in Fig. 14 (c). Magnetic field distribution of all cases is illustrated in Fig. 15 (a), Fig. 15 (b), Fig. 15 (c), and Fig. 15 (d), respectively. Table XXII shows the value of  transmission, table XXIII shows the value of the Contrast  Ratio, and table XXIV shows the value the modulation depth. The contrast ratio is medium because the contrast between ( 56789:(;<=) ) and ( 56789>>(;?@) ) is not large enough. Thus, the performance of this proposed gate is moderate. The modulation depth is very high because the variance between the maximum transmission in ON state and the minimum transmission in OFF state is very large. As a result, the dimensions of the proposed design are excellent and optimum.

IV. COMPARISON BETWEEN THE PROPOSED WORK AND PREVIOUS WORKS
The comparison criteria between this work and previous works are summarized in the table XXV, which shows that the design proposed in this work has better performance than other designs in previous works according to its size, number of plasmonic logic gates, operating wavelength, and augmented transport in some states of some logic gates.

V. CONCLUSION
In this paper, small-dimensional design (300 nm × 300 nm) was proposed. The proposed design capable of implementing seven logic gates (NOT, AND, OR, NAND, NOR, XOR, XNOR) using (2D-FEM) with maximum transmission 134% in NOT gate, 223% in OR gate, 134% in NAND gate and 223% in XNOR gate where the design is optimum based on modulation depth equation. the proposed design was created by (IMI). The gates were implemented at the wavelength of 1550 nm. The mechanism of the gate's work depends on the characteristic of the coupling between the nanoring and the strips. We can implement each gate by changing the position of the ports, the state of the ports and the angle of the transmission light. The design efficiency and performance of the gates were measured by three criteria: transmission, contrast ratio and modulation depth. The proposed transmission threshold is a criterion for distinguishing between OFF and ON state in the output ports. Finally, the proposed design contributes in building nanocircuits for optical signal processing and integrated photonic circuits.